The present invention relates to a fault detection system which can be incorporated into individual integrated circuit chips. In particular, the fault detector of the present invention can detect internal as well as interconnect faults of various types between integrated circuit chips. A particular application of the present invention is an interconnect fault detector for large-scale integrated circuit (LSI) chips and the system connecting a plurality of such chips.
As the various integrated circuit technologies mature, integrated circuit chips are becoming more reliable. As a result, a large percentage of failure detection mechanisms are shifting attention away from the active circuit area within the chip and focusing additionally on the signal interconnect system for a number of chips on a logic card or on various logic cards. The individual circuit chips are becoming such that manufacturing yield is higher. This is why the interconnect system is a current focus of attention for fault reliability or fault detection. Because of the increasing user pressure to improve reliability of products incorporating such chips, a means of detecting a substantial number of the interconnect related failure modes in a system is required. A primary goal of such an interconnect fault detection system is that it can operate simultaneously and continuously with the intended normal circuit operations and functions.
There are several U.S. Patents which are pertinent to the present invention. Perhaps the most pertinent patent known is U.S. Pat. No. 4,183,460 which is directed to a test circuit for current mode logic (CML) chips. The present invention is directed to emitter coupled logic (ECL) chips. There is therefore a clear difference between the present invention and the way it operates in connection with ECL circuits and the patented invention and the way it deals with CML circuits. First, referring to the patent, each chip has a separate input open detector in a separate configuration from the output short detector. The present invention shows a common voltage level sensor circuit used with both output pins and input pins of ECL chips.
Also, the input open detector of the patented invention requires more than one reference voltage to operate. In the present invention, a single reference voltage is applied in connection with all level sensors associated with either input pins or output pins on a chip. Referring to FIG. 2 of the patented invention, the detecting circuit consisting of transistors T3 and T4 undergoes a switching operation as voltage swings from high to low values. The voltage level sensor of the present invention consists of a single transistor device which does not undergo a switching function during voltage swings. The fault detecting function of the patented invention occurs with a switching operation between transistors T5 and T6 shown in FIG. 2 and is represented as a comparison between two different reference voltages. The present invention uses a plurality of level sensors associated with pins on a chip and in which each level sensor device is connected to a fault detect logic bus which is finally connected with a comparator circuit which receives the input reference voltage. The single comparator circuit functions to provide a fault detection report when appropriate.
Thus, the present invention shows a single comparing circuit employing the reference voltage while the patented invention shows a comparing function associated with a transistor switching operation for each input pin and in which the distribution of reference voltages must be made to each such input open detector. The present invention enjoys the advantage the distribution of reference voltages needs to be made to only a single device per chip. There are numerous other differences but it is clear that the present invention is different from the patented invention. It is believed that the present invention provides for a considerable improvement in efficiency in fault detection on LSI chips where a common level sensor circuit can be used for input and output pins and in which a common comparator functions for fault detection for all circuits on the chip. More such differences will become apparent from reading the following specification of the present invention.
One of the reasons that a single circuit design which performs both the open and the short detection functions on inputs as well as outputs represents a significant improvement in connection with the present invention is as follows. Recall first that U.S. Pat. No. 4,183,460 requires a different circuit for short detection than that which performs open detections. In the present invention in which use with gate array integrated circuits is contemplated, the level sensors can be integrated into the gate array matrix before the customized metallization layers are applied to the circuit. Thus, the level sensor circuits according to the present invention which are the same for input pins as for output pins can be created in the chip prior to the definition of exactly which pins will become, in the final circuit, input pins and which will become output pins. The patented invention requires a determination at the beginning the manufacturing process of which pins will become input pins or output pins. Thus the present invention enjoys the advantage of greater flexibility in chip design. Further, there is better utilization of the silicon area in a chip according to the present invention because no extra work is required for logic designers or for automatic placement and routing software tools in chip fabrication because all input and output pins are treated the same regardless of function. In the present invention it is not necessary to detect shorts between two output pins as in the patented invention. This is because it is common to tie output pins of ECL logic gates together to form logical " AND" or "OR" functions of the connected outputs. These events should not be flagged as a short circuit because they are intentional. However, it is still necessary to retain the function of determining if there is a short to ground condition. The present invention accomplishes this end result. The invention in U.S. Pat. No. 4,183,460 only accomplishes the short to ground detection function in connection with the short between two output pin function.
Another pertinent patent is U.S. Pat. No. 4,176,258. The subject patent shows an error checking system which is designed primarily to check the logic of various chips. If the outputs from a first chip and a second chip are checked with respect to one another, an error signal is generated if the two signals do not correspond. Thus, the system is designed to check logic rather than input and output levels or such things as short circuits and open circuits. In fact, if both chips as shown in the subject patent had the same signal, even if erroneous, no error signal would be generated. The present invention, however, generates an error detection signal for short circuits or open circuits or an impedance mismatch signal sufficient to generate a ringing signal outside of the error threshold. Such a signal could of course be generated even if the logic components of a chip were working properly.
U.S. Pat. Nos. 3,851,161; 4,009,437 and 4,241,307 show various test and analysis schemes related to chip interconnections or continuity testing methods. However, all of these patents are related to schemes involving a logic module not in its normal operating mode but in some special test mode. The present invention relates to an error detection system which functions on a logic module while in a conventional operating mode providing a useful logic function in a system. Thus, the subject patents do not anticipate the present invention because the function is related only to a test mode. In addition, none of the three referenced patents shows a single level sensor circuit associated with each input and output pin on a chip all of which are connected to a single comparator per chip to provide a fault detection signal.